1. Field of the Invention
The present invention relates to methods and systems for cache coherence in distributed shared memory (DSM) multiprocessor systems.
2. Background Art
Computer systems, including uni-processor computer systems and multiprocessor computer systems, typically run multiple processes or threads at a time. Each process requires some amount of physical memory. Often, physical memory is limited and must be allocated among the different processes.
Computer systems typically employ one or more levels of cache memory between main memory and each processor in order to reduce memory access time. Cache memories store information that is retrieved from main memory. Information that is retrieved by a processor must pass through one or more levels of cache in order to get to the processor. Because caches tend to be small and physically close to the processor, sometimes located on-chip with the processor, cached information can generally be accessed much faster than information that is stored in main memory. Thus, caches are typically used to store information that needs to be repeatedly accessed by a processor.
Systems and methods for maintaining cache consistency include directory protocols, where the status of memory is maintained in a centralized directory. Information can be cached in multiple locations by different processes that “share” the information. Alternatively, one process may obtain “exclusive” rights to the information for a period of time. When a process changes information, either in main memory or in a cache location, other instances of the information must be invalidated or updated. This is referred to as maintaining cache consistency. In a distributed shared memory (DSM) system, the directory can be distributed. A centralized controller is responsible for maintaining consistency of shared information. Any time that information stored in a memory location is changed, a check is performed in the centralized directory to determine whether a copy of the information is stored in a cache. If so, each copy is either updated or invalidated.
In large DSM multi-processing systems, maintaining cache coherence can be difficult task. DSM systems typically employ a sharing vector to identify where the information is cached. However, as the size of the DSM system increases (e.g., number of processes or processing nodes), the sharing vector subsequently grows larger, reducing processing speed and increasing the amount of time during which the information in cache is unavailable to other processors. Therefore, there is a need for a better system of maintaining cache coherence in DSM multiprocessor systems.